The present invention relates to semiconductor memory devices with improved production yields.
With the increase of memory capacity in the fabrication of recent semiconductor memory devices, the probability of the occurrence of error bit cells has also increased. Conventionally, semiconductor memory devices containing error bit cells have been discarded as defective devices. The discarding of the defective devices is very uneconomical, and also leads to an increase in the manufacturing cost. Some measures taken to solve this problem have succeeded in overcoming such uneconomical manufacturing methods. One of the successful measures employs a memory device with a redundancy function. Specifically, an auxiliary memory is used in addition to a main memory. When the main memory contains an error bit cell, a drive or select line, on which bit cells including the error bit are arranged, is selected and all of the bit cells including the error bit cell are replaced with the correct bit cells arrayed on a select line of the auxiliary memory.
FIG. 1 shows in block form an example of such a semiconductor memory device. In FIG. 1, reference numeral 1 designates an address buffer whose output is applied to a main address decoder 2 and an auxiliary decoder 3. The output signal from the main address decoder 2 is applied to a main memory 4 to select one of the row lines in the main memory 4. Subsequently, data may be written, by a write signal, into specified memory bit cells connected to the selected row line. Similarly, the data may be read out therefrom by a read signal. The main address decoder 2 is controlled by an output signal from the auxiliary address decoder 3. The decoder output of the auxiliary address decoder 3 is applied to an auxiliary memory 5. The signal selects one row line of the auxiliary memory 5. Then, data may be written into memory cells connected to the row line by a write signal, and read out therefrom by a read signal. The auxiliary address decoder 3 is programmed so as to produce an output signal representing an address of a memory area containing an error bit cell in the main memory.
A control signal generating circuit 6 generates a control signal for the auxiliary decoder 3 when an error bit cell is found in the main memory 4. The control signal controls the auxiliary address decoder 3 so as to replace a specific number of bit cells including the error bit cell with the corresponding number of correct bit cells in the auxiliary memory 5. The specific number of bit cells are those arrayed on a select or drive line, having the error bit cell connected thereto, of the main or auxiliary memory. This circuit 6 is composed of a nonvolatile memory, so programmed that it drives the auxiliary address decoder 3 to access the auxiliary memory 5 when the error bit cell is found.
When the main memory 4 does not contain an error bit cell, this control circuit 6 does not operate, and the main address decoder 2 accesses the main memory 4.
On the other hand, when the main memory 4 has an error bit cell and is accessed, the control signal generating circuit 6 drives the auxiliary address decoder 3 to access the auxiliary memory 5, and at the same time to stop the operation of the main address decoder 2. In this way, the error bit cell in the main memory 4 is replaced with the correct bit cell of the auxiliary memory 5.
FIGS. 2A and 2B show practical circuit diagrams of two examples of the control signal generator 6. In the circuit shown in FIG. 2A, a fuse element F made of polysilicon or the like is inserted between a power source VD terminal and an output terminal OUT. A programming enhancement type MOS transistor 7 is connected between the output terminal OUT and a ground. A depletion type MOS transistor 8 is inserted between the output terminal OUT and a ground. A programming signal P is applied to the gate of the MOS transistor 7. The gate of the MOS transistor 8 is connected to a ground. In the circuit shown in FIG. 2B, the power source VD and the output terminal OUT have a programming enhancement type MOS transistor 7 and a depletion type MOS transistor 8, which are connected in parallel therebetween. A fuse element F is inserted between the output terminal OUT and a ground. A programming signal P is applied to the gate of the MOS transistor 7 and the gate of the MOS transistor 8 is connected to the output terminal OUT.
In the circuit shown in FIG. 2A, when the fuse element F is not burned out, a signal level at the output terminal OUT is logical "1" since the resistance ratio of the MOS transistor 8 and the fuse element F is very large. However, when it is burned out, the output terminal OUT is grounded through the MOS transistor 8 and becomes logical "0". In order to burn out the fuse element F, a programming signal P of logical "1" is applied to the gate of the MOS transistor 7. Then, the MOS transistor 7 turns on to allow a large current to flow into the fuse element F. The large current generates Joule heat which in turn burns out the fuse element F. When the fuse element F is burned out, the signal P returns to logical "0" to turn off the transistor 7. The signal at the output terminal OUT, or the control signal from the control signal generator 6, is logical "1", for example, and at this time the decoding operation of the auxiliary address decoder 3 stops. The decoding operation is performed only when the signal at the output terminal OUT is logical "0".
In the circuit of FIG. 2B, when the fuse element F is not burned out, the signal level at the output terminal OUT is kept at logical "0", unlike the circuit of FIG. 2A, since the resistance ratio of the MOS transistor 8 and the fuse element F is very large. On the other hand, when it is burned out, the output terminal OUT is connected to the power source VD terminal through the MOS transistor 8, and is logical "1". In order to burn the fuse element F, a programming signal P of logical "1" is applied to the gate of the MOS transistor 7. At this time, the transistor 7 is turned on, as in the above case, to allow a large current to flow into the fuse element F. In this circuit, when the signal at the output terminal OUT, or a control signal, is logical "0", the decoding operation of the auxiliary address decoder 3 is stopped. When it is logical "1", the decoding operation is executed.
FIG. 3 shows a circuit diagram of an example of the auxiliary address decoder 3 when the control signal generator 6 is not used. The auxiliary address decoder 3 is comprised of a depletion type MOS transistor 9 for a load, a plurality of enhancement type MOS transistors 10 for driving the auxiliary memory whose gates are coupled with an address signal or data A0, A0, . . . , An, An, and a plurality of fuse elements FB inserted between each of the transistors 10 and the transistor 9.
The auxiliary address decoder 3 is so programmed that when the memory cell in the main memory 4 which is specified by an address signal A0=Al=. . . =An=0, is an error bit cell, the decoder 3 produces a signal designating this address. This programming is done by burning the fuse elements FB connected to the transistors 10 coupled with the address signals A0 to An. The auxiliary address decoder 3 thus programmed responds to the address signal A0=Al=. . . =An=0 to access the auxiliary memory 5.
In the auxiliary address decoder 3 shown in FIG. 3, in order to access the auxiliary memory 5, a plurality of fuse elements FB must be burned out, which are selected according to the code of the address signal applied thereto. A laser beam or Joule heat is used to burn out these fuse elements. This burning means, has some problems, however: welded material attached to its peripheral circuit reduces the reliability of the memory device, the failure of burning causes erroneous programming, and reliability on the burned locations is poor. In this respect, it is evident that the fewer the burning locations of the fuse elements, the better. With the remarkable progress of recent microelectronics technology, memory capacity has increased together with the number of bits of an address input signal. Accordingly, the number of fuse elements burned out in the auxiliary memory also increases. For this reason, there is a pressing need to solve the above problems.
There is another method for solving this error bit cell problem of the main memory. In this method, when an error bit cell is found in a memory area specified by, for example, at the most significant bit (MSB) An=0 in the address signal, the MSB An of an address signal from the address buffer is fixed at "0" or "1" irrespective of the contents of the input address signal to the address buffer. The main memory is used as a memory with half the capacity of the main memory having no error bit cell. According to this measure, when an error bit cell is contained in the memory of 16 kilo bits, for example, it can be used as a memory of 8 kilo bits by fixing the MSB of the output address signal from the address buffer at "1" or "0".
FIG. 4 shows a memory array of a memory of 16 kilo bits. The upper half of the memory array is selected by the MSB of the address signal An="0" and the lower half area by the MSB An="1". It is assumed that the memory bit cell at point X is defective in FIG. 4. If the MSB An is fixed at "0", An="0", the memory area specified by An="1" and containing the error bit cell is not selected. Thus, the memory of 16 kilo bits can be used as a memory of 8 kilo bits. A practical arrangement of an address decoder for fixing the MSB An of an address signal at "0", which has thus far been used, is illustrated in FIG. 5. This circuit is an address buffer of the type which receives an address signal An and produces address signals An and An. In FIG. 5, when the control signals F1 and F2 are both "1", MOSFETs 11 and 12 are both turned on. The input address signal An is inverted by an inverter 15 composed of a load MOSFET 13 and a drive MOSFET 14. The inverted signal is again inverted by an inverter 18 composed of a load MOSFET 16 and a drive MOSFET 17 to be an inverted address signal An. This address signal is further applied to an inverter 21 composed of a load MOSFET 19 and a drive MOSFET 20 to be an address signal An. In case where the address buffer is applied for the above-mentioned memory array, if an error bit cell is found in the memory area selected by An="1", a control signal F1 is set to "0" and another control signal F2 is set to "1". In this condition, the MOSFET 11 is always in an OFF state, so that An is "1" and An="0". If the input address signal An to the address buffer takes any logical level, the error bit cell is not selected.
As described above, the main memory containing the error bit cell can be used as a memory having only half the capacity of the main memory, by fixing the MSB of the output signal from the address buffer at "1" or "0". Therefore, the production yield of the memory devices is improved.
The method mentioned above, in which the MSB of the output address signal is fixed at "1" or "0", is ineffective when error bit cells are present in both the memory areas selected by the MSB An="0" and "1", for example, in the memory area hatched and denoted as Y in FIG. 4. The same thing is true for a case in which the error bit memory is located at point Z in the area selected by the MSB An="0" and at point Z' selected by the MSB An="1".
Thus, the circuit as shown in FIG. 5 can only cope with a defective memory in which the error bit cell is located at the memory area selected by the MSB An="0" or "1". Thus, this circuit still involves the problem of low production yield.